Foundations for oxide breakdown compact modeling towards circuit-level simulations

Abstract

Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown. Then a transistor-level model is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and ring oscillator frequency is discussed.