D. Siljenberg, S. Baumgartner, T.C. Buchholtz, M. Maxson, T. Timpane, Jeff Johnson
{"title":"Xbox360 Front Side Bus - A 21.6 GB/s End-to-End Interface Design","authors":"D. Siljenberg, S. Baumgartner, T.C. Buchholtz, M. Maxson, T. Timpane, Jeff Johnson","doi":"10.1109/ASPDAC.2007.358095","DOIUrl":null,"url":null,"abstract":"With a bandwidth of 21.6 GB/s, the front side bus (FSB) of the Microsoft Xbox360trade is one of the fastest, commercially available front side bus interfaces in the consumer market. This paper explains the end-to-end system approach used in designing the bus that achieved volume production ramp 18 months after design start. The 90 nm SOI-CMOS CPU and 90 nm bulk CMOS GPU designs are described. The chip carrier, circuit board, and signal integrity analyses are described. The design approach used to achieve high volume, low cost, and short development time is explained.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"327 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Asia and South Pacific Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2007.358095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
With a bandwidth of 21.6 GB/s, the front side bus (FSB) of the Microsoft Xbox360trade is one of the fastest, commercially available front side bus interfaces in the consumer market. This paper explains the end-to-end system approach used in designing the bus that achieved volume production ramp 18 months after design start. The 90 nm SOI-CMOS CPU and 90 nm bulk CMOS GPU designs are described. The chip carrier, circuit board, and signal integrity analyses are described. The design approach used to achieve high volume, low cost, and short development time is explained.