Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits

Abstract

This paper presents a summary of a unified compact I/sub ds/ model for deep-submicron (DSM) MOSFET's developed from scratch over the past few years. The model covers the full range of gate-length (down to the threshold roll-off region) and biases for a given technology, which requires minimum measurement data to extract its 28 fitting parameters following a prioritized two-iteration sequence. The model has been implemented in an automated extraction program (DOUST), which can be used in aiding new technology development, and in predicting process effects on ULSI circuit performance when implemented in the circuit simulator (XSIM).