Model Calibration of InGaAs/InP p-I-n Test Structures

Abstract

Numerical device model calibration of InGaAs/InP double-heterostructure p-I-n junctions is performed at room temperature using guarded test structures of various areas and investigating the contributions from minority carrier diffusion, depletion region generation and finally perimeter (shunt) leakage. The perimeter leakage is determined to be 0.5 pA/cm, whereas the depletion region contributes 2.2 nA/cm2; the bulk diffusion contribution is excluded via the guard ring but can be computed analytically to be 2.0 nA/cm2. Reproducing the experimental test structures within the numerical modeling environment accurately reproduces the data based on calibrating the diffusion length and SRH lifetime.