Testing DSM asic with static, /spl delta/IDDQ, and dynamic test suite: implementation and results

Abstract

This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, \DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of \DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, \DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.