{"title":"Different physical effects in UDSM MOSFET for delay & power estimation: A review","authors":"A. Singh, J. Samanta","doi":"10.1109/SCEECS.2012.6184747","DOIUrl":null,"url":null,"abstract":"Short-channel effects play a major role for MOS scaling of gate length down and especially below 0.1μm or even less. In this paper, the detail review of different secondary effects and their solutions for delay & power estimation which are proposed by various researchers in the past decade are presented briefly. Different effects like Gate Direct Tunneling Current (GDTC), Gate-Induced Drain Leakage (GIDL), Band-to-Band Tunneling Currents (BTBT), Negative Bias Temperature Instability (NBTI), Polysilicon-Gate Depletion Effects, Velocity Saturation, Reverse Short Channel Effect (RSCE), Substrate Current Induced Body Effect (SCBE), STI Stress Effect and Bulk Charge Effect etc are clearly explained and also described their solution techniques basically in ultra deep submicron region of CMOS devices. Some simulation & experiments results are taken from different researchers which will be explained, how these effects are related to different MOS model parameters.","PeriodicalId":372799,"journal":{"name":"2012 IEEE Students' Conference on Electrical, Electronics and Computer Science","volume":"18 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Students' Conference on Electrical, Electronics and Computer Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCEECS.2012.6184747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Short-channel effects play a major role for MOS scaling of gate length down and especially below 0.1μm or even less. In this paper, the detail review of different secondary effects and their solutions for delay & power estimation which are proposed by various researchers in the past decade are presented briefly. Different effects like Gate Direct Tunneling Current (GDTC), Gate-Induced Drain Leakage (GIDL), Band-to-Band Tunneling Currents (BTBT), Negative Bias Temperature Instability (NBTI), Polysilicon-Gate Depletion Effects, Velocity Saturation, Reverse Short Channel Effect (RSCE), Substrate Current Induced Body Effect (SCBE), STI Stress Effect and Bulk Charge Effect etc are clearly explained and also described their solution techniques basically in ultra deep submicron region of CMOS devices. Some simulation & experiments results are taken from different researchers which will be explained, how these effects are related to different MOS model parameters.