Fast Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H. 264/AVC

Abstract

In this paper a fast processing architecture for the transform and quantization of the H.264/AVC, named DQ engine, is proposed. Compare with the traditional architecture, proposed DQ engine architecture could achieve 2 times fast processing of transform and quantization together with the inverse transform and inverse quantization when the rate-distortion optimization is performed. Moreover, proposed architecture introduced an all-zero block detection architecture which could cut down the redundant processing of the all-zero coefficient blocks. A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits. Implementation results show that the proposed architecture could be fulfilled with only 126,728 transistors.