The Analysis and Metric Algorithm of Delay in Reversible Network

Abstract

Delay is an important parameter that needs to be considered in the reversible logic designs, but not much work on delay in reversible network has been done at present. This paper presents an algorithm to calculate delay of reversible network. In the process of calculating delay, we not only take the complexity of different logic gates into consideration, but also the relationship between the output delay of the target bits and all inputs delay of the controlled reversible logic gates is considered. We use the algorithm to calculate the delay in reversible logic circuits synthesized and optimized by several different reversible logic synthesis methods. Then we analyze the performance of these reversible logic synthesis methods in delay level. Through the comparative analysis, we prove that these reversible logic synthesis methods for some function in reducing quantum cost have a good effect, but not in delay level. The quantum cost of some reversible logic circuits which have the same function is less, however the delay may not.