A low power clock network placement framework

Abstract

Register placement has fundamental influence to a clock network size/wirelength as a clock routing is carried out based on register locations. This paper presents a novel low-power clock placement framework which is independent of placement algorithms. Inspired by the algorithm of Divide and Conquer, the set of whole clock sinks is divided into many subsets and the optimization is mainly carried out in each subset. Since it is impossible to build a complete clock tree during the placement, our approach tries to construct the main topology of the clock tree by bi-partition. In order to cover timing issues, the net-based timing-driven technique by net weighting method is used for achieving a good timing. For characterizing this framework, it is embedded into a force-directed placement flow. Experimental results show the clock network wirelength reduced by 17.18% .