A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation

已完结 10 由 bit5i54 发布于 2025/12/11 16:35:53

DOI:10.1109/IMW56887.2023.10145931
作者：Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai
文献类型：期刊论文
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Institute of Electrical and Electronics Engineers (IEEE)

Abstract：Continuous shrinking of dynamic random access memory $\langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HA

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