最大化随机多路加法器的精度及其在滤波器设计中的应用

T. Baker, J. Hayes
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引用次数: 6

摘要

随机计算(SC)是一种低成本的计算范式,在数字滤波器设计、图像处理和神经网络中有着广阔的应用前景。这些应用程序的基础是加权加法操作,它通常由多路复用器(mux)树实现。基于多路加法器的面积非常小,但当求和数量很大时,通常需要很长的比特流才能达到实际的精度阈值。在这项工作中,我们首先确定了多加法器误差的主要贡献者。然后,我们通过分析和实验证明了精确采样和完全相关两种新技术可以针对并减轻这些误差源。在硬件中实现这些技术导致了CeMux(相关增强多路复用器)的设计,这是一种随机多路加法器,比传统加权加法器更精确,占用的面积更小。在采用大型数字滤波器的心电图滤波案例研究中,我们将CeMux与其他SC和混合设计进行了比较。一个主要的结果是CeMux即使对于大的输入尺寸也是准确的。CeMux的更高精度导致延迟比其他设计减少4到16倍。此外,CeMux比现有设计减少了约35%的面积,并且我们证明了少量的精度可以换取进一步减少50%的面积。最后,我们将CeMux与传统的二进制设计进行了比较,我们发现CeMux可以在与传统设计相似的功耗和延迟下实现50%到73%的面积减少,但误差水平略高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design
Stochastic computing (SC) is a low-cost computational paradigm that has promising applications in digital filter design, image processing, and neural networks. Fundamental to these applications is the weighted addition operation, which is most often implemented by a multiplexer (mux) tree. Mux-based adders have very low area but typically require long bitstreams to reach practical accuracy thresholds when the number of summands is large. In this work, we first identify the main contributors to mux adder error. We then demonstrate with analysis and experiment that two new techniques, precise sampling and full correlation, can target and mitigate these error sources. Implementing these techniques in hardware leads to the design of CeMux (Correlation-enhanced Multiplexer), a stochastic mux adder that is significantly more accurate and uses much less area than traditional weighted adders. We compare CeMux to other SC and hybrid designs for an electrocardiogram filtering case study that employs a large digital filter. One major result is that CeMux is shown to be accurate even for large input sizes. CeMux's higher accuracy leads to a latency reduction of 4× to 16× over other designs. Furthermore, CeMux uses about 35% less area than existing designs, and we demonstrate that a small amount of accuracy can be traded for a further 50% reduction in area. Finally, we compare CeMux to a conventional binary design and we show that CeMux can achieve a 50% to 73% area reduction for similar power and latency as the conventional design but at a slightly higher level of error.
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