{"title":"具有独立双门控结构的多晶硅纳米线场效应管在非易失性存储器应用中的潜力","authors":"Wei-Chen Chen, Horng-Chih Lin, Tiao-Yuan Huang","doi":"10.1109/SNW.2010.5562550","DOIUrl":null,"url":null,"abstract":"A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (IDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":" 14","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications\",\"authors\":\"Wei-Chen Chen, Horng-Chih Lin, Tiao-Yuan Huang\",\"doi\":\"10.1109/SNW.2010.5562550\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (IDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":\" 14\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562550\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562550","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications
A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (IDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.
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