动态可重构计算:大规模缺陷率下同质多核的替代方案

IF 3 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
M. Pereira, L. Carro
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引用次数: 4

摘要

CMOS技术的积极扩展增加了密度,并允许将多个处理器集成到单个芯片中。尽管基于MPSoC架构的解决方案可以通过利用TLP来提高应用程序的速度,但正如Amdahl定律所证明的那样,这种加速仍然受到应用程序中可用并行性的限制。此外,随着设备功能的不断缩小,新技术的缺陷率预计会非常高。在高缺陷率的情况下,MPSoC的大量处理器将容易出现缺陷,从而导致失效,不仅降低了成品率,而且严重影响了预期性能。本文提出了一种运行时自适应架构,即使在高缺陷率下也允许软件执行。所提出的体系结构不仅可以加速高度并行的应用程序,还可以加速顺序应用程序,并且它是一种异构解决方案,可以克服在高缺品率下同构mpsoc所带来的性能损失。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can increase application's speed through TLP exploitation, this speedup is still limited to the amount of parallelism available in the application, as demonstrated by Amdahl's Law. Moreover, with the continuous shrinking of device features, very aggressive defect rates are expected for new technologies. Under high defect rates a large amount of processors of the MPSoC will be susceptible to defects and consequently will fail, not only reducing yield but also severely affecting the expected performance. This paper presents a run-time adaptive architecture that allows software execution even under aggressive defect rates. The proposed architecture can accelerate not only highly parallel applications but also sequential ones, and it is a heterogeneous solution to overcome the performance penalty that is imposed to homogeneous MPSoCs under massive defect rates.
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来源期刊
International Journal of Reconfigurable Computing
International Journal of Reconfigurable Computing COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
1.50
自引率
0.00%
发文量
2
审稿时长
33 weeks
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