低电平缓冲SDRAM控制器

2016 3rd International Conference on Information Science and Control Engineering (ICISCE) Pub Date : 2016-07-08 DOI:10.1109/ICISCE.2016.37

T. Jin, Wenxin Li, Xiangyu Hu

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引用次数: 1

摘要

随着处理器和SDRAM性能的不断提高，SDRAM控制器的性能成为制约系统性能的瓶颈。本文提出了一种低电平缓冲SDRAM控制器，并对其设计和验证进行了描述。该控制器在一定程度上提高了SDRAM存储器处理器的吞吐量，为高性能系统的设计提供了一种解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Tow-Level Buffered SDRAM Controller

With the improvement of processor and SDRAM performance, the performance of SDRAM controller becomes the bottleneck of the system performance. In this paper, a Tow-Level Buffered SDRAM controller is proposed, and its design and verification are described. To some extent, the controller improves the throughput of the processor for the SDRAM memory, and provides a solution for the design of high performance system.

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2016 3rd International Conference on Information Science and Control Engineering (ICISCE)

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