65nm技术中用于逆向工程保护的阈值定义伪装门

Anirudh Iyengar, Deepak Vontela, Ithihasa Reddy Nirmala, Swaroop Ghosh, Seyedhamidreza Motaman, Jaedong Jang
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引用次数: 8

摘要

由于知识产权(IP)逆向工程(RE)恶意获取的威胁日益增加,逻辑门的伪装变得非常重要。在本文中,我们展示了基于晶体管阈值电压定义开关[2]的伪装逻辑门的实验演示,该逻辑门可以隐藏六种逻辑功能,即NAND, AND, NOR, OR, XOR和XNOR。提议的门可用于设计IP,迫使攻击者对底层功能执行暴力猜测和验证——增加了RE的工作量。我们提出了两种伪装方式,一种只采用通通晶体管(nmos开关),另一种采用全通通晶体管(cmos开关)。伪装门用于设计ST 65nm技术的环形振荡器(RO),每种功能一个,我们对其进行了温度,电压和工艺变化分析。我们观察到基于cmos开关的伪装门提供了比基于nmos开关的门更高的性能(约1.5-8倍),而增加的面积成本仅为5%。所提出的门显示功能直到0.65V。我们还能够通过动态改变开关栅电压来恢复失去的性能,并表明在较低电压和温度波动下可以实现稳健的工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection
Due to the ever-increasing threat of Reverse Engineering (RE) of Intellectual Property (IP) for malicious gains, camouflaging of logic gates is becoming very important. In this paper, we present experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities i.e. NAND, AND, NOR, OR, XOR and XNOR. The proposed gates can be used to design the IP, forcing an adversary to perform brute-force guess-and-verify of the underlying functionality---increasing the RE effort. We propose two flavors of camouflaging, one employing only a pass transistor (NMOS-switch) and the other utilizing a full pass transistor (CMOS-switch). The camouflaged gates are used to design Ring-Oscillators (RO) in ST 65nm technology, one for each functionality, on which we have performed temperature, voltage, and process-variation analysis. We observe that CMOS-switch based camouflaged gate offers a higher performance (~1.5-8X better) than NMOS-switch based gate at an added area cost of only 5%. The proposed gates show functionality till 0.65V. We are also able to reclaim lost performance by dynamically changing the switch gate voltage and show that robust operation can be achieved at lower voltage and under temperature fluctuation.
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