H. Miyaoka, Futoshi Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, H. Yamaguchi, Toshihiko Mori, Y. Koyanagi, H. Tamura, Yutaka Ide, Kazuhiro Terashima, H. Higashi, Tomokazu Higuchi, N. Naka
{"title":"一种28.3 Gb/s 7.3 pJ/bit的28 nm CMOS眼采样相位自适应35 dB背板收发器","authors":"H. Miyaoka, Futoshi Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, H. Yamaguchi, Toshihiko Mori, Y. Koyanagi, H. Tamura, Yutaka Ide, Kazuhiro Terashima, H. Higashi, Tomokazu Higuchi, N. Naka","doi":"10.1109/VLSIC.2016.7573472","DOIUrl":null,"url":null,"abstract":"28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"62 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS\",\"authors\":\"H. Miyaoka, Futoshi Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, H. Yamaguchi, Toshihiko Mori, Y. Koyanagi, H. Tamura, Yutaka Ide, Kazuhiro Terashima, H. Higashi, Tomokazu Higuchi, N. Naka\",\"doi\":\"10.1109/VLSIC.2016.7573472\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"62 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573472\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573472","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS
28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).
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