缓存相干多核架构下实时操作系统的设计与评价

G. Gracioli, A. A. Fröhlich
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引用次数: 19

摘要

实时任务在多核处理器中不受控制地使用缓存层次结构可能会影响它们的最坏情况执行时间。为了提高可预测性,最近提出了几种操作系统技术来处理多处理器中的缓存,例如缓存分区、缓存锁定和实时调度。然而,由缓存一致性协议引起的争用及其对实时任务的影响仍然是一个悬而未决的问题。在本文中,我们提出了一个用于缓存相干多核架构的实时操作系统的设计和评估。实时操作系统基础结构包括实时调度器、缓存分区和通过硬件性能计数器检测缓存一致性争用。我们根据运行时开销、实时任务的可调度性、缓存分区性能和硬件性能计数器可用性来评估实时操作系统。我们的研究结果表明:(i)与打过补丁的操作系统相比,从头开始设计的实时操作系统减少了运行时开销,从而提高了实时可调度性;(ii)缓存分区减少了共享缓存中的争用,提供了安全的实时边界;(iii)硬件性能计数器可以检测实时任务何时在共享缓存级别相互干扰。调度、缓存分区和硬件性能计数器一起是在缓存一致架构中提供实时边界的一步。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On the Design and Evaluation of a Real-Time Operating System for Cache-Coherent Multicore Architectures
The uncontrolled use of the cache hierarchy in a multicore processor by real-time tasks may impact their worst-case execution times. Several operating system techniques have been recently proposed to deal with caches in a multiprocessor in order to improve predictability, such as cache partitioning, cache locking, and real-time scheduling. However, the contention caused by the cache coherence protocol and its implication for real-time tasks is still an open problem. In this paper, we present the design and evaluation of a real-time operating system for cache-coherent multicore architectures. The real-time operating system infrastructure includes real-time schedulers, cache partitioning, and cache coherence contention detection through hardware performance counters. We evaluate the real-time operating system in terms of run-time overhead, schedulability of realtime tasks, cache partitioning performance, and hardware performance counters usability. Our results indicate that: (i) a real-time operating system designed from scratch reduces the run-time overhead, and thus improves the realtime schedulability, when compared to a patched operating system; (ii) cache partitioning reduces the contention in the shared cache and provides safe real-time bounds; and (iii) hardware performance counters can detect when real-time tasks interfere with each other at the shared cache level. Scheduling, cache partitioning, and hardware performance counters together are a step-forward to provide real-time bounds in cache-coherent architectures.
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