An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopy

This paper proposes a novel architecture of time-to-digital converter (TDC) with wide input range in polar demodulators for electrical impedance spectroscopy (EIS) systems. The system combines a counter-based TDC with cascaded time interpolation stages and efficiently quantizes the phase component. The maximum phase error of 0.52 degrees from 1-kHz to 2.048-MHz frequency sweep range superior to previously reported ones. Reconfigurability of interpolation factor and cascaded architecture greatly enhances hardware efficiency of the system with average power consumption of 1.93 mW, which makes this work worth for system-on-chip (SoC) realization of EIS systems based on polar demodulators.