海报:探索3D堆叠矢量缓存的设计空间-使用传统EDA工具设计3D堆叠矢量缓存

Ryusuke Egawa, J. Tada, Yusuke Endo, H. Takizawa, Hiroaki Kobayashi
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引用次数: 0

摘要

虽然通过硅通孔(tsv)的3D集成技术有望在未来的微处理器设计中克服内存和功率墙问题,但目前还没有有前途的EDA工具来设计3D集成vlsi。此外,三维集成对微处理器设计的影响还没有得到很好的讨论。在这种情况下,本文提出了利用现有EDA工具设计三维堆叠式高速缓存的方法,并给出了矢量处理器三维堆叠式高速缓存的早期性能评价。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA Tools
Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
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