A 5-6.2GHz Variable Bandwidth Frequency Synthesizer for IEEE 802.11ac Applications

This paper presents a Phase Locked Loop (PLL) circuit designed for IEEE 802.11ac applications with the frequency range of 5GHz to 6.2GHz. In order to have a wide frequency range and to keep the basic parameters of the PLL constant, a control unit is required. The proposed control circuit has two calibration sections; the first part is the frequency calibration, which determines the value of the digital code in the capacitor bank of the Voltage Controlled Oscillator (VCO), and the second part is the Charge Pump (CP), which measures the amount of the VCO gain (KVCO) and consequently changes the CP current flow to provide a fixed Bandwidth (BW). The main circuit of a PLL with an integer divider are implemented in a standard 0.18µm CMOS technology. This PLL, considering the time needed for calibration, is locked up within a period of 12.5µs. Phase noise ratio has been improved to the value of 1.3dBc/Hz by using the calibration circuit. The power consumption of the systems is 13.89mW at the supply voltage of 1.8V.