器件级、电路级和块级的四磁道库中CFET的评估

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI:10.23919/VLSIT.2019.8776513

P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta

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引用次数: 21

摘要

互补FET (cet)的结构是NMOS堆叠在PMOS之上，固有地产生标准单元和SRAM单元，其布局面积比FinFET小25%，引脚密度高25%，布线灵活性高2倍，但总体有源占地面积相同。此外，基于先进的建模，我们的工作表明，4磁道CFET可以匹配甚至优于5磁道FinFET;无需将S/D接触电阻率降低到$5\text{e}-10\Omega。\text{cm}^{2}$或将通道应力提高到2GPa。电路级功率性能区域的所有增益都保持在块级，使4磁道CFET成为N3和N2技术的合适候选人。关键词:CFET，缩放，S/D工程，pi栅极

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Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5\text{e}-10\Omega.\text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.

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2019 Symposium on VLSI Technology

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