一个可重构的大部分数字ΔΣ ADC，最坏情况FOM为160dB

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243842

Gerry Taylor, I. Galton

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引用次数: 29

摘要

提出了一种基于0.075 mm2 65 nm CMOS vco的ΔΣ调制器ADC，该ADC工作于单个0.9-1.2 V电源。它的采样率fs在1.3-2.4 GHz范围内可调，SNDR范围为70-75 dB，带宽范围为5-37.5 MHz，最小SNDR + 10 log(带宽/功耗)优值(FOM)为160 dB。

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A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB

A 0.075 mm² 65 nm CMOS VCO-based ΔΣ modulator ADC that operates from a single 0.9-1.2 V supply is presented. Its sample-rate, f_s, is tunable from 1.3-2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR + 10 log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.

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2012 Symposium on VLSI Circuits (VLSIC)

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