A Low-Noise Stacked Differential Optical Receiver in 0.18-μm CMOS

A stacked differential optical receiver architecture with excellent noise performance is proposed in this paper. By DC coupling two single-ended transimpedance amplifiers (TIA) to the cathode and anode of the photodiode (PD) respectively, and stacking them in voltage domain, differential operation is formed. This not only enables input-referred noise reduction from the differential input scheme, but also simplifies power management design and facilitates power reduction. As a proof of concept, a stacked differential 10Gb/s optical receiver is implemented in a mature 0.18-µm CMOS technology, demonstrating the feasibility of the proposed architecture. The optical receiver achieves differential gain of 68.4dBΩ, 6GHz of -3-dB bandwidth and state-of-the-art input-referred noise current of 7.2pA/√Hz while consuming 83mW from a single 3.3V power supply.