Development of a Cryogenic System for the Characterization of Advanced CMOS technologies down to 350 mK

In this manuscript, we present an experimental setup capable to extract main electrical parameters and thermal effects from semiconductor devices within a range of temperatures from 300 K down to 350 mK. Key aspects of the system such as sample holder design and wire material selection, are discussed. One of the most critical design limitations is the maximum thermal power handling, since at sub-Kelvin temperatures the cooling power is limited by a3He4He fridge. The largest amount of heat transferred into the system comes from the electrical wiring, is reduced by the combined use of Copper and Manganin wires. This way we reach an optimized balance between electrical resistance and heat conduction. Therefore we ensure the DUT reaches the Ultra-Cold Stage (UCS) temperature while the electrical measurements are minimally affected by the electrical resistance. Under this condition the cryogenic system allows a reliable electrical characterization of a 14 nm SOI p-FinFET down to 350 mK.