用于60GHz收发器锁相环的δ - σ分数n分频器

2011 IEEE International Conference of Electron Devices and Solid-State Circuits Pub Date : 2011-12-29 DOI:10.1109/EDSSC.2011.6117645

Yisheng Wang, Kaixue Ma, N. Mahalingam, K. Yeo

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引用次数: 3

摘要

介绍了锁相环数字δ - σ分数n分频器的设计与优化流程。低功耗设计用于采用0.18um SiGe BiCMOS技术的60 GHz射频收发器。充分考虑到锁相环的低复杂度和无条件稳定性，选择MASH111 δ - σ调制器作为锁相环的控制模块。输入频率为6.48Ghz，整数分割率为36 ~ 64，步长为2。

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A delta-sigma fractional-N frequency divider for a Phase Lock Loop in 60GHz transceiver

A design and optimization flow for digital delta-sigma fractional-N frequency divider of Phase Lock Loop (PLL) is introduced in this paper. The low power design is used for the 60 GHz RF transceiver using 0.18um SiGe BiCMOS technology. With full consideration of the low complexity and unconditional stability, MASH111 delta-sigma modulator is chosen as control module for the PLL. The input frequency is 6.48Ghz, and the integer division rate is from 36 to 64 with step of 2.

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2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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