并行存储信道的相关噪声估计与误差校正

M. Varsamou, I. Zacharias, T. Antonakopoulos
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引用次数: 0

摘要

新技术的发展常常导致需要以新的方式表述老问题。基于mems的存储系统使用多个同时访问的信道,其设计必须面对不同信道中相关噪声的问题。这项工作提出了一种利用这种通信/存储系统中固有的并行性来估计相关误差向量并改进数据解码过程的方法。该方法利用多信道的并行性,利用初始错误解码尝试所显示的错误位置将符号标记为擦除,并估计引入的信道噪声向量,并为所有信道的解调器提供软信息。数值结果表明,所提出的方法提高了性能,从而提高了此类系统/设备的可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Correlated noise estimation and error correction in parallel storage channels
The evolution of new technologies frequently results to the need of formulating old problems in new way. The design of MEMS-based storage systems that use multiple, simultaneously accessed channels, has to confront, among others, the problem of correlated noise in different channels. This work presents a method that exploits the inherent parallelism found in such communication/storage systems in order to estimate the correlated error vector and to improve the data decoding process. The method uses the parallelism of the multiple channels both to flag symbols as erasures using the error locations revealed by the initial errors-only decoding attempt, and to estimate the introduced channel noise vector and provide soft information to the demodulators of all channels. Numerical results demonstrate the performance improvement that is achieved by the proposed method, thus improving the reliability of such systems/devices.
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