{"title":"探索机器学习在异构多处理器上的线程表征","authors":"Cha V. Li, V. Petrucci, D. Mossé","doi":"10.1145/3139645.3139664","DOIUrl":null,"url":null,"abstract":"We introduce a thread characterization method that explores hardware performance counters and machine learning techniques to automate estimating workload execution on heterogeneous processors. We show that our characterization scheme achieves higher accuracy when predicting performance indicators, such as instructions per cycle and last-level cache misses, commonly used to determine the mapping of threads to processor types at runtime. We also show that support vector regression achieves higher accuracy when compared to linear regression, and has very low (1%) overhead. The results presented in this paper can provide a foundation for advanced investigations and interesting new directions in intelligent thread scheduling and power management on multiprocessors.","PeriodicalId":7046,"journal":{"name":"ACM SIGOPS Oper. Syst. Rev.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Exploring Machine Learning for Thread Characterization on Heterogeneous Multiprocessors\",\"authors\":\"Cha V. Li, V. Petrucci, D. Mossé\",\"doi\":\"10.1145/3139645.3139664\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We introduce a thread characterization method that explores hardware performance counters and machine learning techniques to automate estimating workload execution on heterogeneous processors. We show that our characterization scheme achieves higher accuracy when predicting performance indicators, such as instructions per cycle and last-level cache misses, commonly used to determine the mapping of threads to processor types at runtime. We also show that support vector regression achieves higher accuracy when compared to linear regression, and has very low (1%) overhead. The results presented in this paper can provide a foundation for advanced investigations and interesting new directions in intelligent thread scheduling and power management on multiprocessors.\",\"PeriodicalId\":7046,\"journal\":{\"name\":\"ACM SIGOPS Oper. Syst. Rev.\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACM SIGOPS Oper. Syst. Rev.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3139645.3139664\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM SIGOPS Oper. Syst. Rev.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3139645.3139664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploring Machine Learning for Thread Characterization on Heterogeneous Multiprocessors
We introduce a thread characterization method that explores hardware performance counters and machine learning techniques to automate estimating workload execution on heterogeneous processors. We show that our characterization scheme achieves higher accuracy when predicting performance indicators, such as instructions per cycle and last-level cache misses, commonly used to determine the mapping of threads to processor types at runtime. We also show that support vector regression achieves higher accuracy when compared to linear regression, and has very low (1%) overhead. The results presented in this paper can provide a foundation for advanced investigations and interesting new directions in intelligent thread scheduling and power management on multiprocessors.