基于总线的片上系统通信架构的快速性能分析

K. Lahiri, A. Raghunathan, S. Dey
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引用次数: 59

摘要

本文讨论了高效和准确的性能分析问题,以推动基于总线的片上系统(SOC)通信架构的探索和设计。我们的技术填补了现有系统级性能分析技术的空白,这些技术要么太慢,无法在迭代通信架构设计框架中使用(例如,完整系统的模拟),要么不够精确,无法驱动通信架构的设计(例如,执行系统性能静态分析的技术)。提出的系统级性能分析技术包括:在硬件/软件分区和映射之后进行初始联合仿真,组件之间的通信以抽象的方式建模(例如,作为事件或数据传输);提取抽象的符号轨迹,表示为总线和同步事件(BSE)图,捕获各种系统组件的活动及其随时间的通信;以及使用总线参数对BSE图进行操作,以导出考虑总线体系结构影响的系统行为。我们给出了几个示例系统的实验结果,包括一个TCP/IP网络接口卡子系统。结果表明,我们的性能估计技术比执行完整的系统模拟快两个数量级以上,同时非常准确(从精确的硬件/软件联合模拟中得出的性能估计在2.2%以内)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based system-on-chip (SOC) communication architectures. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system), or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a static analysis of the system performance). The proposed system-level performance analysis technique consists of: initial co-simulation performed after HW/SW partitioning and mapping, with the communication between components modeled in an abstract manner (e.g., as events or data transfers); extraction of abstracted symbolic traces, represented as a bus and synchronization event (BSE) graph, that captures the activity of the various system components and their communication over time; and manipulation of the BSE graph using the bus parameters, to derive the behavior of the system accounting for effects of the bus architecture. We present experimental results on several example systems, including a TCP/IP network interface card sub-system. The results indicate that our performance estimation technique is over two orders of magnitude faster than performing a complete system simulation, while being very accurate (within 2.2% of performance estimates derived from accurate HW/SW co-simulation).
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