一个事件驱动的无别名ADC，具有信号依赖的分辨率

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243773

Colin Weltin-Wu, Y. Tsividis

{"title":"一个事件驱动的无别名ADC，具有信号依赖的分辨率","authors":"Colin Weltin-Wu, Y. Tsividis","doi":"10.1109/VLSIC.2012.6243773","DOIUrl":null,"url":null,"abstract":"A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"30 1","pages":"28-29"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"An event-driven, alias-free ADC with signal-dependent resolution\",\"authors\":\"Colin Weltin-Wu, Y. Tsividis\",\"doi\":\"10.1109/VLSIC.2012.6243773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"30 1\",\"pages\":\"28-29\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 28

摘要

130nm CMOS的无时钟8b ADC采用时变比较窗口来动态改变分辨率和输入相关的动态偏置，在保持SNDR的同时节省功耗。在20kHz带宽和3-9μW功率下，在0.8V电源下实现了47-54dB范围内的无误操作，SNDR部分超过了传统转换器8b的理论极限。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An event-driven, alias-free ADC with signal-dependent resolution

A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2012 Symposium on VLSI Circuits (VLSIC)

自引率

0.00%

发文量