A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-domain time-interleaved (TI) SAR ADC [1]–[2] is a popular choice for its superior power efficiency. However, its single-channel sample rate is generally limited to <1GS/s, necessitating a large number of TI channels in high-sample-rate scenarios. It inevitably increases implementation overhead, including capacitive loading to the input driver and total area consumption. Recently, time-domain ADCs [3]–[5] have shown promising sampling speed, but are mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR TDCs [6] demonstrate a lower complexity but are generally limited in sample rate (MS/s). In this work, we propose a two-step time-domain ADC that uses a first-stage Flash TDC with the residue time quantized by the second-stage SAR TDC, targeting the >GS/s regime. To further improve the throughput of SAR TDC conversion, we propose a delay-tracking pipelining technique that allows the SAR TDC to quantize two residue time samples, simultaneously. At the circuit level, we use a selective delay tuning (SDT) cell to provide the time reference required for SAR conversion without using an excessive number of delay stages. A proof-of-concept ADC prototype in 14nm CMOS technology with 2x time interleaving achieves 10GS/s with 37.2dB SNDR at Nyquist frequency. It measures an energy efficiency of 24.8fJ/conv-step and occupies an active area of 2850um2, which are the highest reported energy efficiency and smallest area consumption among the state-of-the-art ADCs with> 10GS/s [7].