一种线性0.18um CMOS分布低噪声放大器，频率为3.1至10.6 GHz，带级联单元

2010 International Conference on Enabling Science and Nanotechnology (ESciNano) Pub Date : 2010-12-01 DOI:10.1063/1.3586976

S. Shamsadini, F. Kashani, Neda Bathaei

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引用次数: 1

摘要

在本文中，我们提出了一种3.1-10.6GHz超宽带(UWB)分布式低噪声放大器的设计方法，该放大器采用标准台积电0.18um CMOS技术。四个单元DLNA，每个单元包含级联编码架构，可用于宽带应用。所提出的分布式低噪声放大器在3.1-10.6 GHz全频段内具有合适的输入输出匹配。我们在3.1至10.6GHz范围内获得了12dB (S21)的平坦功率增益，在整个UWB频段内纹波仅为±0.3 dB，从而获得了可接受的低噪声放大器结果。所提出的DLNA具有良好的线性特性。该DLNA的第三个截距点(IIP3)为+2dBm, P1dBin为- 12dBm。输入阻抗匹配为<−15 dB (S11)，输出阻抗匹配为<−15db (S22)在整个频带。该LNA的最小噪声系数为2.8dB。

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A linear 0.18um CMOS Distributed Low Noise Amplifier from 3.1 to 10.6 GHz with cascode cells

In this paper, we propose a design methodology of 3.1–10.6GHz Ultra-wideband (UWB) Distributed Low Noise Amplifier using standard TSMC 0.18um CMOS technology. The four cells DLNA, each cell contains cascode architecture, can be use in broadband applications. The proposed distributed low noise amplifier has an appropriate input and output matching over the full band of 3.1–10.6 GHz. We achieve acceptable results for low noise amplifier as a flat power gain of 12dB (S21) from 3.1 to 10.6GHz, which is ripple only ±0.3 dB over the full UWB band. The proposed DLNA has an excellent linear behavior. The third intercept point (IIP3) of the proposed DLNA is +2dBm and P1dBin is −12dBm. An input impedance matching is <−15 dB (S11) and an output impedance matching of < −15 dB (S22) over the entire band. This LNA achieves the minimum noise figure of 2.8dB.

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2010 International Conference on Enabling Science and Nanotechnology (ESciNano)

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