具有优越硬件效率的全相干形状偏移QPSK解调器结构

D. Rieth, C. Heller, G. Ascheid
{"title":"具有优越硬件效率的全相干形状偏移QPSK解调器结构","authors":"D. Rieth, C. Heller, G. Ascheid","doi":"10.1109/APCCAS.2016.7803924","DOIUrl":null,"url":null,"abstract":"Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"168-171"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency\",\"authors\":\"D. Rieth, C. Heller, G. Ascheid\",\"doi\":\"10.1109/APCCAS.2016.7803924\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.\",\"PeriodicalId\":6495,\"journal\":{\"name\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"13 1\",\"pages\":\"168-171\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2016.7803924\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803924","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

形状偏移QPSK (SOQPSK)是一种高带宽效率的恒定包络波形。为了提高硬件和能源效率,提出了一种适用于连续模式和突发模式传输的全相干SOQPSK解调架构。它包含频率、相位和时间偏移的决策导向(DD)同步环路,以及基于嵌套巴克码的鲁棒帧开始(SoF)检测和相位模糊解决(PAR)相结合的低复杂度方法。粗粒度管道结构的目标是最小化时钟速度和能耗,同时保持高总体吞吐量。通过无乘法器匹配滤波器(MF)设计,可以大大降低复杂度。计算机仿真和现场可编程门阵列(FPGA)实现结果表明,在接近最佳误码率(BER)性能方面,复杂性和精度之间的权衡得到了合理的选择,与文献中的实现相比,硬件效率提高了90%以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency
Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.
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