{"title":"用于MCM封装的压阻式加速度计","authors":"J. Plaza, A. Collado, E. Cabruja, J. Esteve","doi":"10.1109/JMEMS.2002.805213","DOIUrl":null,"url":null,"abstract":"Describes the first steps carried out for the integration of piezoresistive accelerometers in an MCM-D (D-type multichip modules with flip-chip interconnection) package. The bulk micromachined accelerometer technology and its modification to comply with MCM-D packaging technology requirements are presented. The accelerometer technology is based on BESOI (Bond and Etch Back Silicon-On-Insulator) wafers. The main characteristic of this technology is the use of the buried silicon oxide layer as an etch stop and as a sacrificial layer. In addition, over-range protection and self-test systems are defined without any additional photolithographic step or process. The flip chip attachment requires solderable metals in the bump pads. In addition, a sealing ring has been defined around the movable parts of the sensors to protect them from the underfill used during the final packaging process. Cantilever beam accelerometers with a self-test system are presented as example of the combined technology. The design, simulation, fabrication and characterization of the devices prior to the MCM-D packaging are presented as well.","PeriodicalId":13438,"journal":{"name":"IEEE\\/ASME Journal of Microelectromechanical Systems","volume":"29 1","pages":"794-801"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"54","resultStr":"{\"title\":\"Piezoresistive accelerometers for MCM package\",\"authors\":\"J. Plaza, A. Collado, E. Cabruja, J. Esteve\",\"doi\":\"10.1109/JMEMS.2002.805213\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Describes the first steps carried out for the integration of piezoresistive accelerometers in an MCM-D (D-type multichip modules with flip-chip interconnection) package. The bulk micromachined accelerometer technology and its modification to comply with MCM-D packaging technology requirements are presented. The accelerometer technology is based on BESOI (Bond and Etch Back Silicon-On-Insulator) wafers. The main characteristic of this technology is the use of the buried silicon oxide layer as an etch stop and as a sacrificial layer. In addition, over-range protection and self-test systems are defined without any additional photolithographic step or process. The flip chip attachment requires solderable metals in the bump pads. In addition, a sealing ring has been defined around the movable parts of the sensors to protect them from the underfill used during the final packaging process. Cantilever beam accelerometers with a self-test system are presented as example of the combined technology. The design, simulation, fabrication and characterization of the devices prior to the MCM-D packaging are presented as well.\",\"PeriodicalId\":13438,\"journal\":{\"name\":\"IEEE\\\\/ASME Journal of Microelectromechanical Systems\",\"volume\":\"29 1\",\"pages\":\"794-801\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"54\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE\\\\/ASME Journal of Microelectromechanical Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/JMEMS.2002.805213\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE\\/ASME Journal of Microelectromechanical Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/JMEMS.2002.805213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 54
摘要
介绍将压阻式加速度计集成到MCM-D(带倒装互连的d型多芯片模块)封装中的第一步。介绍了本体微机械加速度计技术及其为满足MCM-D封装技术要求而进行的改进。加速度计技术基于BESOI (Bond and Etch Back Silicon-On-Insulator)晶圆。该技术的主要特点是使用埋置氧化硅层作为蚀刻停止层和牺牲层。此外,超量程保护和自检系统的定义无需任何额外的光刻步骤或过程。倒装芯片附件需要在凸垫中焊接金属。此外,在传感器的可移动部件周围定义了一个密封圈,以保护它们免受最终包装过程中使用的下填料的影响。以悬臂梁式加速度计和自检系统为例,介绍了这种组合技术。介绍了MCM-D封装前器件的设计、仿真、制造和表征。
Describes the first steps carried out for the integration of piezoresistive accelerometers in an MCM-D (D-type multichip modules with flip-chip interconnection) package. The bulk micromachined accelerometer technology and its modification to comply with MCM-D packaging technology requirements are presented. The accelerometer technology is based on BESOI (Bond and Etch Back Silicon-On-Insulator) wafers. The main characteristic of this technology is the use of the buried silicon oxide layer as an etch stop and as a sacrificial layer. In addition, over-range protection and self-test systems are defined without any additional photolithographic step or process. The flip chip attachment requires solderable metals in the bump pads. In addition, a sealing ring has been defined around the movable parts of the sensors to protect them from the underfill used during the final packaging process. Cantilever beam accelerometers with a self-test system are presented as example of the combined technology. The design, simulation, fabrication and characterization of the devices prior to the MCM-D packaging are presented as well.