F. Khan, D. Moy, D. Anand, E. Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata
{"title":"将逻辑晶体管转变为安全,多时间可编程,嵌入式非易失性存储器元件,用于14纳米FINFET技术及以后","authors":"F. Khan, D. Moy, D. Anand, E. Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata","doi":"10.23919/VLSIT.2019.8776510","DOIUrl":null,"url":null,"abstract":"Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $< 50\\%$ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"22 1","pages":"T116-T117"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond\",\"authors\":\"F. Khan, D. Moy, D. Anand, E. Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata\",\"doi\":\"10.23919/VLSIT.2019.8776510\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $< 50\\\\%$ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"22 1\",\"pages\":\"T116-T117\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776510\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776510","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond
Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $< 50\%$ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.