一种8位70 mhz CMOS数模转换器,具有两级电流单元矩阵结构

Ji Hyun Kim, K. Yoon
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引用次数: 2

摘要

本文介绍了一种8位70 mhz CMOS数模转换器(DAC),其两级电流单元矩阵结构由一个4msb电流矩阵级和一个4lsb电流矩阵级组成。两级电流单元矩阵架构允许设计的DAC不仅降低了解码逻辑的复杂性,而且减少了电流源的数量。采用该架构可实现快速的建立时间和低功耗的DAC。仿真结果表明,在3.3 V单电源下,最大转换率为70 MHz,功耗为24.5 mW,芯片尺寸为0.8 mm/spl倍/1.0 mm的CMOS 1.5 /spl mu/m n阱技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 8-bit 70-MHz CMOS digital-to-analog converter with two-stage current cell matrix structure
This paper describes an 8-bit 70-MHz CMOS digital to analog converter (DAC) with two stage current cell matrix structure which is composed of a 4 MSB current matrix stage and a 4 LSB current matrix stage. The two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of the decoding logic, but also the number of current sources. Fast settling time and low power consumption of the DAC are achieved by utilizing the proposed architecture. The simulation results show that the maximum conversion rate is 70 MHz, the power dissipation is 24.5 mW with a single power supply of 3.3 V, and the chip size is 0.8 mm/spl times/1.0 mm for a CMOS 1.5 /spl mu/m n-well technology.
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