Bi-Transfer: A Data Packet Allocation Module with Chaining Transmission Mode

With the increasing performance requirements of network data interaction on chip, the traditional Direct Memory Access (DMA) often performs with low efficiency of multi-module collaboration due to the competition of bus control, thereby reducing the throughput rate of the bus. Aiming at the working characteristics of inter-core communication and data interaction between multiple modules, this paper designs a packet transmission module Bi-Transfer that supports bidirectional data flow between multiple modules It also realizes chaining transmission of input and output data in parallel with various configuration modes and flexible data scheduling modes. This module can complete the functions of data movement, inter-core communication, task management, etc., and use descriptors to link load data packets to uniformly conFigure the data interaction mode of the on-chip network. In the experimental stage, function planning and code design are carried out first, then the timing simulation and data recording are described. Finally, the performance characteristics of this new data interaction module are discussed. According to statistical observations, increasing the number of channels in the design module can significantly increase the bandwidth of the bus. Under the given clock frequency, bus width and data transmission requirements, the bus operating bandwidth in the four-channel working mode can reach up to 4690 MB/s at most, which is nearly 400 MB/s beyond the ordinary DMA bus bandwidth. In the case of fewer channels, this module can fulfill the data scheduling requirements of most applications and provide the data moving function of ordinary DMA.