低k对串扰的影响[深亚微米技术]

G. Servel, D. Deschacht, Françoise Saliou, J. Mattei, F. Huret
{"title":"低k对串扰的影响[深亚微米技术]","authors":"G. Servel, D. Deschacht, Françoise Saliou, J. Mattei, F. Huret","doi":"10.1109/ISQED.2002.996757","DOIUrl":null,"url":null,"abstract":"With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Impact of low-k on crosstalk [deep sub-micron technologies]\",\"authors\":\"G. Servel, D. Deschacht, Françoise Saliou, J. Mattei, F. Huret\",\"doi\":\"10.1109/ISQED.2002.996757\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.\",\"PeriodicalId\":20510,\"journal\":{\"name\":\"Proceedings International Symposium on Quality Electronic Design\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2002.996757\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2002.996757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

随着深亚微米技术中导线间距的减小,耦合电容变得越来越重要。这种容量的增加会产生能够传播逻辑故障的噪声。对串扰的不良评估可能是电路故障的根源。封闭形式的公式在确定设计规则方面特别有效。从串扰评估的解析表达式出发,我们探讨了在深亚微米技术的上金属能级的给定典型几何形状下,通过不同的层内介质获得的性能增益。该模型预测,通过使用等于2的低k介电介质,可以将串扰电压降低约25%,这可以用于可能减少线间距。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impact of low-k on crosstalk [deep sub-micron technologies]
With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信