基于8.865 ghz−244dB-FOM高频压电谐振器的亚ppb级级分数n锁相环

S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu
{"title":"基于8.865 ghz−244dB-FOM高频压电谐振器的亚ppb级级分数n锁相环","authors":"S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu","doi":"10.1109/VLSIC.2016.7573548","DOIUrl":null,"url":null,"abstract":"This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"31 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique\",\"authors\":\"S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu\",\"doi\":\"10.1109/VLSIC.2016.7573548\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"31 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573548\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文提出了一种基于高频压电谐振器(PZR)的级联分数n锁相环,该锁相环采用亚ppb阶频率分辨率的通道调节技术,克服了使用窄幅GHz PZR的困难。此外,利用负电感技术抑制了互连线寄生电感引起的不良振荡。一个节能分频器有助于节省第二个锁相环的功率,抑制输出相位噪声的1ghz参考。原型锁相环采用65nm CMOS制造,输出为8.484GHz至8.912GHz, rmms抖动为180 fs, FOM为-244 dB,功耗为12.7mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique
This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信