电源架构中对事务性内存的健壮架构支持

Harold W. Cain, Maged M. Michael, Brad Frey, C. May, Derek Williams, Hung Q. Le
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引用次数: 127

摘要

在原始出版物发表20周年之际[10],经过十年的激烈研究文献活动,对事务性内存(TM)的硬件支持终于成为商业现实,许多硬件供应商目前或即将提供支持html的芯片。在本文中,我们描述了对Power ISA™未来版本中添加的TM的体系结构支持。有两个必要因素推动了开发:希望用更友好的接口来补充弱一致性的内存模型,以简化多线程应用程序的开发和移植,以及对超出某些早期实现的健壮性的需求。在将该特性商业化的过程中,我们必须解决一些以前未探索过的TM与ISA现有特性之间的交互,例如翻译关闭、中断处理、原子读-修改-写原语以及弱一致性内存模型。我们描述了这些交互、整个体系结构,并讨论了我们选择体系结构语义的动机和基本原理,超出了参考手册中通常找到的内容。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Robust architectural support for transactional memory in the power architecture
On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.
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