Reducing the hardware complexity of a parallel prefix adder

Currently, parallel prefix adders (PPA) are considered effective combinational circuits for performing the binary addition of two multi-bit numbers. These adders are widely used in arithmetic-logic units, which are parts of modern processors, such as microprocessors, digital signal processors, etc. This paper deals with Kogge-Stone adder, which is one of the fastest PPA. When performing the schematic implementation, this adder has a large hardware complexity. Therefore, in this work for reducing its hardware complexity the scheme of modified PPA has been developed. The performance parameters considered for the comparative analysis of the presented adders are: the number of logic gates, Quine-complexity and maximum delay obtained when schematic modeling in CAD environment Quartus II based on FPGA Altera EP2C15AF484C6. As a result, when simulation of 32-bit adder, Kogge-Stone adder and modified PPA have similar maximum delay. However modified PPA has reduced hardware complexity by 22.5% compared to Kogge-Stone adder.