S. Moriwaki, Yasuhiro Yamamoto, A. Kawasumi, Toshikazu Suzuki, S. Miyano, T. Sakurai, H. Shinohara
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A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.
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