具有匹配约束的线负载导向模拟路由

Hao-Yu Chi, C. Liu, Hung-Ming Chen
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引用次数: 3

摘要

随着设计复杂性呈指数级增长,电子设计自动化(EDA)工具对于减少设计工作量至关重要。然而,几十年来,模拟布局设计仍然是手工完成的,因为它是一个敏感和容易出错的任务。由于在非理想效果下的性能损失,工具生成的布局仍然不被模拟设计人员所接受。大多数以前的工作集中在增加更多的布局约束的模拟放置。因此,布线网被认为是一个微不足道的步骤,可以通过典型的数字布线方法来完成,该方法是使用过孔连接每条水平线和垂直线。这些额外的过孔将显著增加导线负载并降低电路性能。因此,本文提出了一种面向线负载的模拟路由方法,以减少每个路由网络的层转换次数。优化目标考虑导线负载,同时考虑导线长度以保证布线后的电路性能,同时布线时仍要满足对称性、长度匹配等模拟布线约束。实验结果表明,该方法显著降低了布线后的导线负载和性能损失,且导线长度开销很小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Wire Load Oriented Analog Routing with Matching Constraints
As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.
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