S. Hwang, Donghoon Yoo, Soojung Ryu, Jeongwook Kim
{"title":"符号位参考波形的高效高吞吐率互关逻辑设计","authors":"S. Hwang, Donghoon Yoo, Soojung Ryu, Jeongwook Kim","doi":"10.1109/ICCE.2013.6486873","DOIUrl":null,"url":null,"abstract":"This paper presents an efficient design method for high throughput rate cross-correlation logic using sign-bit reference waveforms which is one of widely equipped signal processing units in embedded consumer electronic devices. The proposed method minimizes resource usages by efficiently sharing the first level adders in adder trees of parallel sub-logics.","PeriodicalId":6432,"journal":{"name":"2013 IEEE International Conference on Consumer Electronics (ICCE)","volume":"5 1","pages":"234-235"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient high throughput rate cross-correlation logic design for sign-bit reference waveforms\",\"authors\":\"S. Hwang, Donghoon Yoo, Soojung Ryu, Jeongwook Kim\",\"doi\":\"10.1109/ICCE.2013.6486873\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an efficient design method for high throughput rate cross-correlation logic using sign-bit reference waveforms which is one of widely equipped signal processing units in embedded consumer electronic devices. The proposed method minimizes resource usages by efficiently sharing the first level adders in adder trees of parallel sub-logics.\",\"PeriodicalId\":6432,\"journal\":{\"name\":\"2013 IEEE International Conference on Consumer Electronics (ICCE)\",\"volume\":\"5 1\",\"pages\":\"234-235\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference on Consumer Electronics (ICCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2013.6486873\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference on Consumer Electronics (ICCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2013.6486873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient high throughput rate cross-correlation logic design for sign-bit reference waveforms
This paper presents an efficient design method for high throughput rate cross-correlation logic using sign-bit reference waveforms which is one of widely equipped signal processing units in embedded consumer electronic devices. The proposed method minimizes resource usages by efficiently sharing the first level adders in adder trees of parallel sub-logics.