ΔΣ A - D转换器的设计

Electronics and Communications in Japan (Part III: Fundamental Electronic Science) Pub Date : 2007-06-01 DOI:10.1002/ECJC.20269

E. Hayahara, Kenich Aoki, S. Hirano

{"title":"ΔΣ A - D转换器的设计","authors":"E. Hayahara, Kenich Aoki, S. Hirano","doi":"10.1002/ECJC.20269","DOIUrl":null,"url":null,"abstract":"The ΔΣ modulation A-D converter is widely used in practice as a high-resolution A-D converter suitable for LSI implementation. However, in general, if the order of the loop filter in the ΔΣ modulation A-D converter exceeds three, stability of the circuit is no longer guaranteed. In this paper, the relationship of the loop filter coefficients in the A-D converter is studied. Based on the results, a design method is proposed for a higher-order ΔΣ modulation A-D converter such that stability is assured while maximizing the signal-to-noise (SN) ratio. Further, the results of a PSPICE simulation and experimental results obtained using individual components confirm that the present design method is sufficiently practical. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(6): 10– 16, 2007; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/ecjc.20269","PeriodicalId":100407,"journal":{"name":"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)","volume":"10 1","pages":"10-16"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A design of ΔΣ A‐D converter\",\"authors\":\"E. Hayahara, Kenich Aoki, S. Hirano\",\"doi\":\"10.1002/ECJC.20269\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ΔΣ modulation A-D converter is widely used in practice as a high-resolution A-D converter suitable for LSI implementation. However, in general, if the order of the loop filter in the ΔΣ modulation A-D converter exceeds three, stability of the circuit is no longer guaranteed. In this paper, the relationship of the loop filter coefficients in the A-D converter is studied. Based on the results, a design method is proposed for a higher-order ΔΣ modulation A-D converter such that stability is assured while maximizing the signal-to-noise (SN) ratio. Further, the results of a PSPICE simulation and experimental results obtained using individual components confirm that the present design method is sufficiently practical. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(6): 10– 16, 2007; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/ecjc.20269\",\"PeriodicalId\":100407,\"journal\":{\"name\":\"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)\",\"volume\":\"10 1\",\"pages\":\"10-16\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1002/ECJC.20269\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1002/ECJC.20269","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

ΔΣ调制模数转换器作为一种适合大规模集成电路实现的高分辨率模数转换器，在实践中得到了广泛的应用。但是，一般情况下，如果ΔΣ调制模数转换器中环路滤波器的阶数超过三阶，则电路的稳定性不再得到保证。本文研究了模数转换器中环路滤波器系数的关系。在此基础上，提出了一种高阶ΔΣ调制模数转换器的设计方法，在保证稳定性的同时最大限度地提高了信噪比。此外，PSPICE仿真结果和单个元件的实验结果证实了该设计方法的实用性。©2007 Wiley期刊公司电子工程学报，2009,31 (6):1010 - 1016;在线发表于Wiley InterScience (www.interscience)。wiley.com)。DOI 10.1002 / ecjc.20269

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A design of ΔΣ A‐D converter

The ΔΣ modulation A-D converter is widely used in practice as a high-resolution A-D converter suitable for LSI implementation. However, in general, if the order of the loop filter in the ΔΣ modulation A-D converter exceeds three, stability of the circuit is no longer guaranteed. In this paper, the relationship of the loop filter coefficients in the A-D converter is studied. Based on the results, a design method is proposed for a higher-order ΔΣ modulation A-D converter such that stability is assured while maximizing the signal-to-noise (SN) ratio. Further, the results of a PSPICE simulation and experimental results obtained using individual components confirm that the present design method is sufficiently practical. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(6): 10– 16, 2007; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/ecjc.20269

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Electronics and Communications in Japan (Part III: Fundamental Electronic Science)

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