通过路径整形和动态周期调整的变化感知流水线内核:一个浮点单元的案例研究

Ioannis Tsiokanos, L. Mukhanov, Dimitrios S. Nikolopoulos, G. Karakonstantis
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引用次数: 7

摘要

在本文中,我们提出了一个框架,以最大限度地减少流水线设计中变化引起的时序故障,同时限制传统的基于保护带的方案所带来的任何开销。我们的方法最初限制了长延迟路径(llp),并通过塑造路径分布将它们隔离在尽可能少的管道阶段。这样的策略有利于采用一个特殊的单元来预测孤立的llp的激励,并动态地允许只完成这些容易出错的路径的额外周期。此外,我们的框架基于从各种应用程序中提取的实际操作数执行布局后动态时序分析。这使我们能够在考虑动态数据相关路径激励的情况下估计潜在延迟变化下的误码率。当应用于在45nm工艺技术中实现IEEE-754兼容的双精度浮点单元(FPU)时,与参考设计相比,在8%延迟变化下,路径整形有助于将误码率平均降低2.71倍。集成的llp预测单元和动态周期调整避免了此类故障和任何质量损失,其成本高达0.61%的吞吐量和0.3%的面积开销,而与具有悲观边际的FPU相比,平均节省了37.95%的功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit
In this paper, we propose a framework for minimizing variation-induced timing failures in pipelined designs, while limiting any overhead incurred by conventional guardband based schemes. Our approach initially limits the long latency paths (LLPs) and isolates them in as few pipeline stages as possible by shaping the path distribution. Such a strategy, facilitates the adoption of a special unit that predicts the excitation of the isolated LLPs and dynamically allows an extra cycle for the completion of only these error-prone paths. Moreover, our framework performs post-layout dynamic timing analysis based on real operands that we extract from a variety of applications. This allows us to estimate the bit error rates under potential delay variations, while considering the dynamic data dependent path excitation. When applied to the implementation of an IEEE-754 compatible double precision floating-point unit (FPU) in a 45nm process technology, the path shaping helps to reduce the bit error rates on average by 2.71 x compared to the reference design under 8% delay variations. The integrated LLPs prediction unit and the dynamic cycle adjustment avoid such failures and any quality loss at a cost of up-to 0.61% throughput and 0.3% area overheads, while saving 37.95% power on average compared to an FPU with pessimistic margins.
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