技术缩放对CMOS射频器件和电路的影响

E. Abou-Allam, T. Manku, Michele Ting, M. Obrecht
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引用次数: 39

摘要

本文考察了CMOS技术的射频/微波性能与栅极长度的关系。对以下CMOS技术进行了表征和比较:0.18 /spl mu/m、0.25 /spl mu/m、0.35 /spl mu/m、0.5 /spl mu/m和0.8 /spl mu/m。单位电流增益频率标为有效栅极长度上的1。对于nMOS和pMOS晶体管,当栅极长度小于0.5 /spl mu/m时,2.0 GHz时的最小噪声系数小于1.5 dB。对于0.8 /spl mu/m和0.18 /spl mu/m栅极长度,共轭噪声匹配所需的总器件宽度分别为400 /spl mu/m和50 /spl mu/m。对于0.5 /spl mu/m和0.18 /spl mu/m CMOS工艺,1.9 GHz级联LNA所需的电流分别为15 mA和2.7 mA。电流的减少是由于g/sub m//I/sub ds/对于0.18 /spl mu/m的过程是25 V/sup -1/,而对于0.5 /spl mu/m的过程则等于5 V/sup -1/。使用pMOS晶体管的优点在1伏射频前端接收器中得到说明。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impact of technology scaling on CMOS RF devices and circuits
In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 /spl mu/m, 0.25 /spl mu/m, 0.35 /spl mu/m, 0.5 /spl mu/m and 0.8 /spl mu/m. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 /spl mu/m for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 /spl mu/m and 50 /spl mu/m for the 0.8 /spl mu/m and 0.18 /spl mu/m gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 /spl mu/m and 0.18 /spl mu/m CMOS processes, respectively. This reduction in current is due to the fact that g/sub m//I/sub ds/ for a 0.18 /spl mu/m process is 25 V/sup -1/ whereas it is equal to 5 V/sup -1/ for a 0.5 /spl mu/m process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver.
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