采用VLSI技术的低功耗单相时钟分布

A. Indhumathi, A. Sathishkumar
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引用次数: 0

摘要

时钟分配网络消耗了IC消耗的总功率的近70%,因为这是唯一具有最高开关活动的信号。通常对于多时钟域网络,我们会开发多个锁相环来满足需求,本项目旨在开发一个低功耗的单时钟多频带网络,为多时钟域网络提供支持。该项目非常有用,推荐用于蓝牙,Zigbee等通信应用。提出了基于吞脉拓扑的无线局域网频率合成器,采用Verilog对设计进行建模,采用Modelsim进行仿真,并在Xilinx中实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A low power single phase clock distribution using VLSI technology
The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulse-swallow topology and the designed is modeled using Verilog simulated using Modelsim and implemented in Xilinx.
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