Efficient hardware architectures for computation of image moments

Geometric moments are used in numerous image analysis tasks. While several approaches have been proposed, real-time computation is still inefficient. In this paper, a mathematical formulation of the relationship of the all-pole filter output to the geometric moments is discussed. Using this formulation, architectures for implementing in hardware geometric moments of 1, 2 or 3D objects are proposed. Four implementations are programmed in field programmable logic devices (FPGA) devices with typical clock frequencies of 40 MHz. The speed of these devices is adequate for real-time applications, and they can be used to extract local as well as global geometric moments.