A Comparison of Supervised Approaches for Process Pattern Recognition in Analog Semiconductor Wafer Test Data

The semiconductor industry is currently leveraging to exploit machine learning techniques to improve and automate the manufacturing process. An essential step is the wafer test, where each single device is measured electrically, resulting in an image of the wafer. Our work is based on the hypothesis that deviations of production processes can be detected via spatial patterns on these wafermaps. Supervised learning methods are one possibility to recognize such patterns in an automated way - however, the training sample size is very low. In our work, we present and compare several methods for multiclass classification, which can deal with this limitation: multiclass decision trees, as well as decomposition methods like round robin and error-correcting output coding (ECOC). As elementary classifiers, we compare binary decision trees and logistic regression using an elastic net regularization. The evaluation shows that the decomposition methods outperform the multiclass decision tree regarding both, accuracy and practical demands.