{"title":"20gb /s双模SST VCSEL驱动程序","authors":"S. Mahran, O. Liboiron-Ladouceur, G. Cowan","doi":"10.1109/MWSCAS47672.2021.9531803","DOIUrl":null,"url":null,"abstract":"This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"124 1","pages":"428-431"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"20 Gb/s Dual-Mode SST VCSEL Driver\",\"authors\":\"S. Mahran, O. Liboiron-Ladouceur, G. Cowan\",\"doi\":\"10.1109/MWSCAS47672.2021.9531803\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.\",\"PeriodicalId\":6792,\"journal\":{\"name\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"124 1\",\"pages\":\"428-431\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS47672.2021.9531803\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
